The present invention relates to input amplifiers, and more particularly, to input amplifiers that have low noise and low offset output signals and are compatible with standard submicron CMOS processes.
An input amplifier is a type of amplifier that may be used as an input stage for circuit applications such as an operational amplifier or a comparator. FIG. 1 illustrates prior input amplifier 10 comprising transistors made from standard submicron CMOS processes. Input voltage VIN is applied to the bases of PNP bipolar junction transistors (BJTs) QL1 and QL2. BJTs QL1 and QL2 comprise a differential pair amplifier, with a bias current (equal to I) from current source I1 and a single ended output at the gate of n-channel MOSFET M3. The emitters of BJTs QL1 and QL2 are coupled to a current mirror circuit comprising n-channel MOSFETs M1 and M2. The drain of M2 is coupled to the gate of transistor M3. Transistor M3 is a common-source amplifier that provides voltage gain to the input signal to produce output voltage VOUT at the drain of M3. Transistor M3 is biased from current source I2, at a current equal to I.
FIGS. 3A-3B illustrates top down and cross sectional layout views, respectively, of PNP BJTs QL1 and QL2. BJTs QL1 and QL2 are each lateral PNP BJTs that may be fabricated using standard submicron CMOS process steps that are used to fabricate p-channel MOSFETs. Each of BJTs QL1 and QL2 includes a parasitic vertical PNP BJT, QS1 and QS2, respectively, as shown in FIGS. 1 and 3A-3B. The lateral PNP BJTs (QL1 and QL2) and their parasitic vertical PNP BJTs (QS1 and QS2) share the same base and emitter semiconductor regions, but have different collector semiconductor regions as shown in FIGS. 3A-3B. Lateral BJTs QL1 and QL2 each have a collector terminal coupled to a P+ collector region 32 that surrounds a P+ emitter region 31 as shown in FIGS. 3A-3B. Vertical BJTs QS1 and QS2 each have a collector terminal coupled to a P+ region 33 that is tied to the P-substrate region of the device, which is grounded. FIG. 3C illustrates a schematic of the lateral and vertical PNP BJTs of FIGS. 3A-3B.
Referring to FIG. 1, a current equal to I/2 flows through each of transistors QL1 and QL2 when VIN equals zero, assuming that no current flows into transistors QS1, and QS2. Transistor M3 is sized by design so that it has a channel width-to-length (W/L) ratio that is 2 times the channel W/L ratio of n-channel MOSFETs M1 and M2. The W/L ratio of transistor M3 relative to the W/L ratio of transistors M1 and M2 determnines the current through transistor M3. Thus, when I/2 flows through each of transistors M1 and M2, a current equal to I flows through M3, causing VOUT to be accurate with a low signal-to-noise ratio.
However, a significant parasitic current iEQS1 and iEQS2 does flow into the emitters of parasitic transistors QS1 and QS2. The parasitic current causes the current through transistors M1 and M2 to be less than I/2. Because the current through transistor M3 is still I, VDS of M1 and VDS of M2 are no longer equal and the circuit is unbalanced, causing an offset voltage with respect to the amplifier inputs or an inaccurate VOUT. Therefore, transistors QS1, and QS2 cause prior art amplifier 10 to have a systematic offset voltage at VOUT.
It would therefore be desirable to provide a CMOS compatible input amplifier that improves upon prior art input amplifier 10 by reducing output offset to provide a more accurate amplified signal VOUT.
The present invention comprises an input amplifier circuit that provides a low input offset voltage amplified output signal. Input amplifiers of the present invention include a differential pair of transistors that may be fabricated using standard CMOS process steps. Each transistor in the differential pair includes a parasitic transistor that reduces the current through the associated differential pair transistor.
The differential pair has a single ended output coupled to the input of a second amplifier such as a MOSFET. The current through the second amplifier determines the output signal VOUT. The second amplifier is coupled to a third transistor which also includes a parasitic transistor. The third transistor provides a bias current to the second amplifier that is proportional to the current through the differential pair transistors. By providing a proportional current to the second amplifier, input amplifiers of the present invention output an accurate, low input offset voltage amplified signal VOUT.